Anti-Tamper Digital Clocks Fundamentals Explained
Anti-Tamper Digital Clocks Fundamentals Explained
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Consequently, the present invention just isn't intended to be limited to the embodiments revealed herein but will be to be accorded the widest scope in step with the concepts and novel functions disclosed herein.
In other far more specific facets of the invention, Every of the plurality of delayed monotone alerts comprises both a one or possibly a zero. The evaluate circuit may perhaps determine irrespective of whether the amount of ones within the plurality of delayed monotone indicators differs from a h2o amount selection by more than a predetermined threshold.
The water degree range could possibly be decided determined by delayed monotone indicators from one or more former clock Assess time. The plurality of resettable hold off line segments might comprise taps alongside a hold off line. Alternatively, the plurality of resettable hold off line segments comprises parallel delay traces.
Resettable hold off line segments concerning a resettable hold off line segment 210-1 connected to a bare minimum hold off time and a resettable hold off line segment 210-N connected to a most hold off time are Every single associated with discretely escalating delay moments. The Assess circuit 240 is brought on by the clock CLK and uses the plurality of delayed monotone alerts to detect a clock fault.
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sixteen. The apparatus for detecting clock tampering as described in claim fifteen, wherein the resettable hold off line segments are reset during a reset time frame, wherein the reset time frame is just before the clock evaluate time frame.
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34. The apparatus for detecting voltage tampering as described in assert 33, wherein the water level quantity is decided dependant on delayed monotone indicators from one or more earlier Assess time.
19. The equipment for detecting clock tampering as outlined in claim 18, wherein the drinking water amount variety is decided based upon delayed monotone signals from one or more earlier clock Examine time.
24. The strategy for detecting voltage tampering as described in assert 23, further comprising: resetting the resettable delay line segments for the duration of a reset period of time, wherein the reset time frame is previous to the Appraise time period.
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The reset period of time could be just before the clock Consider period of time 310. Using the clock CLK to trigger the evaluate circuit 240 might utilize a clock edge at an finish of your clock Appraise period of time to trigger the evaluate circuit.